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New product development, based on SOC (System on a Chip) and IP (Intellectual Property) cores, requires, as much as possible, design and test [1]. High design productivity drives the need for test preparation to be carried out as early as possible in the design flow, thus at RTL (Register Transfer Level) [2]. However, RT-level test patterns are not routinely reused for production test, since high-quality structural tests require detailed knowledge of the final structural implementation, only available after logic synthesis. Cost effective product development makes use of TRP (Test Resource Partitioning) between the product under development and the target ATE (Automatic Test Equipment), leading to an increased use of BIST (Built-In Self Test) techniques in today SOCs and cores, with builtin sources (TPG, or Test Pattern Generators), TAM (Test Access Mechanisms) and sinks (Signature Analyzers). High quality BIST needs to efficiently tackle the coverage of random-pattern-resistant (r.p.r) defects. This is crucial, as low-cost built-in TPG usually generate PR (Pseudo Random) vectors, through LFSR (Linear Feedback Shift Registers) or CA (Cellular Automata) [3,4]. PR tests usually require extremely long BIST sessions. Several techniques have been proposed to cover r.p.r at logic level [3-5]. These techniques either modify the CUT (Circuit Under Test) by test point insertion, or generate weighted pseudo-random vectors, or introduce mixed-mode test generation. In mixed-mode TPG, deterministic tests are added to PR vectors to detect the r.p.r. faults. e.g., by reseeding an LFSR [6]. Test quality is usually measured by the FC (Fault Coverage) metrics, or more accurately by the DC (Defects Coverage) metrics [7]. FC is usually computed as the percentage of gate-level, single Line Stuck-At (LSA) faults detected by the test pattern. DC is computed as the " percentage of listed defects which are detected by the test pattern. The weighting factor is the relative likelihood of occurrence of the defects, dependent on process line statistics and defects critical area. One key attribute of the quality of the BIST solution is test length, as it directly impacts IP core test application time and the energy required to perform the BIST session [8]. Recently, a novel mixed-mode technique has been proposed to cover r.p.r , referred as "# [9]. The technique, reviewed in section 2, relies on the mask concept. For combinational modules, a " is one partially defined input vector which activates a specific functionality, hard to activate by PR vectors, as the input sub-space for which it is triggered is very limited. techniques allow the coverage of hard to detect faults at given locations of the CUT’s . For each hard fault, one seed is applied once. In contrast to reseeding techniques, the mask-based technique considers the & ( description and targets the coverage of hard to activate . For each hard functionality, one mask is applied, the don’t care bits are filled with PR values (generated by the built-in TPG), and a set of vectors is applied to fully scrutinize the underlying physical structure which implements it, thus uncovering hard defects with few test vectors (see Fig. 1). The mask-based BIST technique exhibits several degrees of freedom, associated with the trade-offs among area